1. Field of the Invention
The present invention relates to the field of data processing and in particular to the storing of a state of a processor prior to entering a low power mode in which the processor is powered down.
2. Description of the Prior Art
It is known to turn a clock off to a processor for periods when no work is required from it. This reduces power consumption, however there are still power losses due to leakage through the silicon. These power losses could be reduced by turning the power off to the core, but this has the drawback that state in the processor may be lost. It is important that when the low power mode is exited, the system should return to its previous state unaltered such that processing operations can continue smoothly and efficiently. It would be highly disadvantageous if information/state was lost during low power mode so as to require a full system reboot and initialisation upon restart. It is known to provide data processing systems in which the system state may be saved and restored.
In order to facilitate this type of power saving during low power mode, it is known to provide power down software routines on data processing systems which are executed when entry to the low power or power down mode is required and which serve to save to some non-volatile storage the state of the system such that a complementary piece of software can be run when the system resumes operation and this state information can be restored from the non-volatile storage. Processing can then be recommenced at the same point and with the same system state. A significant disadvantage with this approach is that the software required to execute the store and restore of state is relatively slow. Furthermore, there may be some system state information which is not accessible to the software responsible for saving the system state, such as for example cache memory contents, tightly coupled memory contents and other relatively low level hardware state information concerning the system. In such circumstances, when processing is resumed, it recommences in a way that only approximates the state of the system when power down occurred. Thus, there may be a requirement to refill all of the cache memories which may be a relatively slow and power consuming operation. Furthermore, on restarting the system some state, such as page table mappings, which is required for a simple restart is not available.
An alternative hardware state saving system is disclosed in patent application GB02395302 to ARM® Cambridge Limited. In this system, scan chains present in the processor are used to extract the state of the processor and this state is then stored to memory. The state can then be restored by using the scan chains to scan the state back in. A disadvantage of this system is that the scan chains scan in and out the entire state of the core and the entire state may not be needed to restore the system following low power mode. Furthermore, use of scan chains in this way needs to be done at implementation time where they will need to be hooked up correctly as well as balanced and controlled appropriately.
It would be advantageous to produce a system of storing and restoring state of a processor without at least some of the disadvantages of the prior art.